article

• 1.6 Gbit/s Real-Time Synchronous QPSK Transmission with Standard DFB Lasers
• 32-krad/s Polarization and 3-dB PDL Tracking in a Realtime Digital Coherent Polarization-Multiplexed QPSK Receiver
• A 200mV 32b Subthreshold Processor with Adaptive Supply Voltage Control
• A 65 nm Standard Cell Library for Ultra Low-power Applications
• A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS
• A Layer Model for Systematically Designing Dynamically Reconfigurable Systems
• A Massively Parallel Architecture for Self-Organizing Feature Maps
• A Multiprocessor Cache for Massively Parallel SoC Architectures
• A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing
• A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems
• A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing
• A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters
• A System Approach for Partially Reconfigurable Architectures
• A Systematic Approach for Optimized Bypass Configurations for Application-specific Embedded Processors
• A TCMS-based architecture for GALS NoCs.
• A design framework for FPGA-based dynamically reconfigurable digital controllers
• A framework for design space exploration of resource efficient network processing on multiprocessor SoCs
• A holistic methodology for network processor design
• A mapping strategy for resource-efficient network processing on multiprocessor SoCs
• A reconfigurable neuroprocessor for self-organizing feature maps
• A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms
• A scalable parallel SoC architecture for network processors
• AXI-based SpaceFibre IP CORE Implementation
• Adaptable Switch boxes as on-chip routing nodes for networks-on-chip
• An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods
• An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems
• Analysis of SEU Effects in Partially Reconfigurable SoPCs.
• Applying dynamic reconfiguration in the mobile robotics domain: a case study on computer vision algorithms.
• Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs
• Bio-inspired massively parallel architectures for nanotechnologies
• Cipset for a Coherent Polarization-Multiplexed QPSK Receiver
• Coherent Digital Polarization Diversity Receiver for Real-Time Polarization-Multiplexed QPSK Transmission at 2.8 Gb/s
• Coherent optical communication: Towards realtime systems at 40 Gbit/s and beyond
• Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI
• Component case study of a self-optimizing RCOS/RTOS system. A reconfigurable network service
• Context Saving and Restoring for Multitasking in Reconfigurable Systems
• CoreVA-MPSoC: A Many-core Architecture with Tightly Coupled Shared and Local Data Memories
• CoreVA: A Configurable Resource-efficient VLIW Processor Architecture
• Data centres for IoT applications: The M2DC approach (Invited paper)
• Dedicated Module Access in Dynamically Reconfigurable Systems
• Defragmentation Algorithms for Partially Reconfigurable Hardware
• Design Optimizations for Tiled Partially Reconfigurable Systems
• Design Optimizations to Improve Placeability of Partial Reconfiguration Modules
• Design Space Exploration for Memory Subsystems of VLIW Architectures
• Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing Applications
• Development of Self-Optimizing Systems
• Dynamic Reconfiguration of Real-Time Network Interfaces
• Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture
• Dynamically Reconfigurable Hardware for Autonomous Mini-Robots
• Dynamically Reconfigurable Hardware – A New Perspective for Neural Network Implementations
• Dynamically reconfigurable hardware for digital controllers in mechatronic systems
• Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.
• Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI
• Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors
• Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems
• FPGA-Based Realization of Self-Optimizing Drive-Controllers
• FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports
• FPGA-based Multi-Robot Tracking
• FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking
• FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications
• Fast Adaptive Polarization and PDL Tracking in a Real-Time FPGA-Based Coherent PolDM-QPSK Receiver
• First Real-Time Data Recovery for SynchroneusQPSK Transmission with Standard DFB Lasers
• Frequency Estimation and Compensation for Coherent QPSK Transmission with DFB Lasers
• Frequency and Phase Estimation for Coherent QPSK Transmission With Unlocked DFB Lasers
• GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications
• GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors
• HIBRIC-MEM, a Memory Controller for PowerPC Based Systems
• Hardware Accelerated Data Analysis
• Hardware Accelerators for Elliptic Curve Cryptography
• Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures
• Hardware-Efficient and Phase Noise Tolerant Digital Synchronous QPSK Receiver Concept
• Hardware-in-the-Loop Simulations for FPGA-Based Digital Control Design.
• High Level Specification of Embedded Listeners for Monitoring of Network-on-Chips
• Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware
• Implementation of artificial neural networks on a reconfigurable hardware accelerator
• M2DC – A Novel Heterogeneous Hyperscale Microserver Platform
• M2DC – Modular Microserver DataCentre with heterogeneous hardware
• Methods of Improving the Dependability of Self-optimizing Systems
• Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.
• Network application driven instruction set extensions for embedded processing clusters
• OLT(RE)²: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems
• On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems
• On-chip interconnects for next generation system-on-chips
• Optimizing inter-FPGA communication by automatic channel adaptation
• PDL-Tolerant Real-time Polarization-Multiplexed QPSK Transmission with Digital Coherent Polarization Diversity Receiver
• Pareto-optimal Signal Processing on Low-Power Microprocessors
• Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux
• Performance Estimation of Streaming Applications for Hierarchical MPSoCs
• Polarization-Multiplexed 2.8 Gbit/s Synchronous QPSK Transmission with Real-Time Digital Polarization Tracking
• Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography
• Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography
• REPLICA2Pro: Task Relocation by Bitstream Manipulation in VIRTEX-II/Pro FPGAs
• REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems
• Real-time Digital Carrier & Data Recovery for a Synchronous Optical Quadrature Phase Shift Keying Transmission System
• Realtime 40 krad/s Polarization Tracking with 6 dB PDL in Digital Synchronous Polarization-Multiplexed QPSK Receiver
• Realtime Optical Synchronous QPSK Transmission with DFB lasers
• Realtime digital polarization and carrier recovery in a polarization-multiplexed optical QPSK transmission
• Realtime multiprocessor for mobile ad hoc networks
• Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications
• Reconfigurable Vision Processing System for Player Tracking in Indoor Sports
• Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve Cryptography
• Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography
• Resource efficiency of the GigaNetIC chip multiprocessor architecture
• Run-Time Reconfiguration of FPGA-Based Drive Controllers
• Run-time reconfigurability in embedded multiprocessors
• Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis
• SOM hardware with acceleration module for graphical representation of the learning process
• Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance
• SelfS – A Real-Time Protocol for Virtual Ring Topologies
• Supplementary Data for the Paper entitled ''An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods''
• Survey of FPGA applications in the period 2000 – 2015 (Technical Report)
• Synchronous QPSK transmission at 1.6 Gbit/s with standard DFB lasers and real-time digital receiver
• System-Level Analysis of Network Interfaces for Hierarchical MPSoCs
• System-on-programmable-chip approach enabling online fine-grained 1D-placement
• Task Placement for Heterogeneous Reconfigurable Architectures
• The Comprehensive MAC Taxonomy Database: comatose
• The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio
• The M2DC Project: Modular Microserver DataCentre
• The Paradigm of Self-optimization
• The Utilization of Reconfigurable Hardware to Implement Digital Controllers: a Review
• Towards Real-Time Implementation of Coherent Optical Communication
• Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks
• vMAGIC - Automatic Code Generation for VHDL